1. Technical Field
This disclosure relates to safe memories having redundant elements. More particularly, the disclosure relates to repair control logic for safe memories wherein the risk of multibit defects is reduced.
2. Discussion of the Related Art
Semiconductor devices are known for high reliability and long operating life. However, reliable and safe operation is critical when human lives depend on the electronic device. Examples of such electronic applications include automobiles and medical devices. In such applications, circuits are designed to minimize the risk of failure to the extent possible.
Electronic devices commonly use a SOC (system on chip) which includes one or more processing devices, one or more memories, input/output circuitry and other circuitry required for a particular application. It is known that memory devices are prone to defects due to local variations in the semiconductor device. A defect in one or more bits of the memory can cause the electronic device to malfunction or fail. As noted, such defects are not acceptable in certain critical applications.
It is known to provide memories with redundant rows and/or columns to allow repair of the memory by inhibiting use of a defective row or column and enabling use of a redundant row or column. A defective row or column may be detected using BIST (built-in self-test) techniques, and the redundant row or column is used in place of the defective row or column.
During operation of the electronic device, error correction techniques may be used to detect errors. An error correction code may be stored with data in the memory and is used to detect an error. Detection of single bit errors is relatively straightforward using known error correction techniques. However, multibit errors are relatively difficult to detect and, in certain applications, may lead to catastrophic results. Accordingly, it is desirable to avoid the use of circuitry which may lead to multibit failures.